1. Field of the Invention
The present invention relates to a fault test apparatus and a fault test method for testing using a predetermined fault excitation function whether or not a fault occurs in a circuit under test that is a semiconductor device such as an LSI chip.
2. Related Art
Following recent development of semiconductor micro-fabrication technique, it has become essential to guarantee product quality and to ensure quick yield. Due to this, it is necessary to guarantee high quality of an entire product (to attain target yield within a product lifetime) and to realize appropriate test cost by analyzing and feeding back a portion of a failure, a cause of the failure, and a statistic behavior of the failure using information obtained from results of a test and a fault diagnosis. In a next-generation chip, such physical failures as scratches or voids due to miniaturization and elongation of wirings, introduction of copper wirings and the like conspicuously appear as a resistive short (bridge fault/short-circuit) between signal lines or as breaking of wirings and vias (open wirings and vias). Those failures or faults are reported to have great influence on the quality and performance of the chip. Fault diagnosis methods and test data generation methods according to prior arts are disclosed in, for example, the following prior art documents:
Patent document 1: Japanese patent laid-open publication No. JP-4-055776-A;
Patent document 2: Japanese patent laid-open publication No. JP-6-194418-A;
Patent document 3: Japanese patent laid-open publication No. JP-10-312406-A;
Patent document 4: Japanese patent laid-open publication No. JP-2006-313133-A;
Patent document 5: U.S. Pat. No. 6,836,856;
Patent document 6: Japanese patent laid-open publication No. JP-8-180095-A;
Patent document 7: Japanese patent laid-open publication No. JP-8-304513-A;
Patent document 8: Japanese patent laid-open publication No. JP-6-259500-A;
Patent document 9: Japanese patent laid-open publication No. JP-2005-140710-A;
Non-patent document 1: W. Chen et al., “Analytic models for crosstalk delay and pulse analysis under non-ideal inputs”, Proceedings of IEEE ITC, pp. 809-818, 1997;
Non-patent document 2: Y. Sato et al., “A persistent diagnostic technique for unstable defects”, Proceedings of IEEE ITC, pp. 242-249, 2002
Non-patent document 3: Y. Sato et al., “Quality Evaluations of Logic BIST's Pseudo Random Patterns”; Transaction on Electronics, IEICE (Institute of Electronics, Information and Communication Engineers), Vol. 87, D-1, No. 1, pp. 35-41, January 2004;
Non-patent document 4: S. Irajpour et al., “Analyzing crosstalk in the presence of weak bridge defects”, Proceedings of IEEE VTS, pp. 385-392, 2003;
Non-patent document 5: R. D. Blanton et al., “Universal test generation using fault tuples”, Proceedings of ITC, 2000;
Non-patent document 6: R. D. Blanton et al., “Fault tuples in diagnosis of deep-submicron circuits”, Proceedings of ITC, 2002;
Non-patent document 7: R. D. Blanton et al., “Analyzing the Effectiveness of Multiple Detect Test Set”, Proceedings of ITC, 2003;
Non-patent document 8: R. D. Blanton et al., “Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction”, Proceedings of VTS, 2005;
Non-patent document 9: R. D. Blanton et al., “Defect Modeling Using Fault Tuples”, IEEE TCAD, 2006;
Non-patent document 10: R. D. Blanton et al., “A Logic Diagnosis Methodology for Improved Localization Extraction of Accurate Defect behavior”, Proceedings of ITC, 2006;
Non-patent document 11: R. D. Blanton et al., “Diagnostic Test Generation for Arbitrary Faults”, Proceedings of ITC, 2006.
Non-patent document 12: Hiroshi Oomura et al., “Testability Evaluation of Open Faults in Consideration of the Voltage of the Adjacent Lines”, Proceedings of Combination conference of Shikoku branches of Electronics related societies, 10-7, pp. 130, September 2005; and
Non-patent document 13: Syuhei Kadoyama et al., “Open fault model with considering adjacent lines and its fault diagnosis”, Technical report of IEICE (Institute of Electronics, Information and Communication Engineers), Vol. 105, No. 607, pp. 25-30, DC2005-76, February 2006.
As the micro-fabrication of the semiconductor process proceeds, it is considered that a logic value change in the bridge fault/short-circuit portion or open portion on the signal line of the device under test turns into an instable fault state because of the dynamic interference between a signal line having a fault (referred to as a fault signal line hereinafter) and a signal line adjacent to the fault signal line. The fault test method based on a single stuck-at fault model according to the prior art is considered insufficient due to these causes.
Next, physical failure modeling and fault test methods in relation to the physical failure modeling will be described.
For example, Non-patent document 1 proposes a crosstalk fault model by paying attention to polarities (directions) of signal transitions in two signal lines (a fault signal line and an adjacent signal line) and a timing skew (timing information) indicating a deviation in signal transition timing between the two signal lines. Similarly, Non-patent document 4 proposes a resistive bridge fault model with paying attention to polarities (directions) of signal transitions in two signal lines (a fault signal line and an adjacent signal line) and a timing skew indicating the deviation in signal transition timing between the two signal lines.
Non-patent document 2 proposes a method of diagnosing an open fault with paying attention to a signal line having the open fault and a signal line adjacent to the fault signal line. In addition, Non-patent document 3 evaluates a random pattern detection capability with respect to open faults.
Moreover, Blanton et al. propose physical fault modeling as well as test generation methods and fault diagnosis methods using the physical fault models as disclosed in Non-patent documents 5, 7 to 11 and Patent document 5. The fault form of each of the fault models proposed by Blanton et al. is expressed by fault tuples constituted by three components including a signal line number, a normal value or a fault value of the signal line, and a test number. Further, Blanton et al. propose a model constituting fault tuples including a fault signal line and adjacent signal lines by extracting signal lines within a certain distance from the fault signal line as the adjacent signal lines based on layout information, as disclosed in Non-patent document 7 and 10.
However, the fault models of the device under test, the test generation methods, and the fault diagnosis methods proposed so far according to the prior arts have the following problems.
(1) As the fault model of the device under test, no fault model has been proposed which is formed with integrally considering the following:
(a) layout information such as the inter-wiring distance between the fault signal line and the adjacent signal line, the parallel distance between the fault signal line and the adjacent signal line, and wiring widths of the signal lines;
(b) manufacturing process information influencing electric characteristics such as distances between wiring layers, wiring materials, and insulating layer materials; and
(c) timing information such as the directions of signal transitions on the signal lines, and the timing window of the signal transitions caused by the dynamic interference.
(2) No test generation method has been proposed which is intended to improve a fault detection ratio for faults of logic value changes due to the dynamic interference of the signal transition on the adjacent signal line.
3) No fault diagnosis method has been proposed which is integrally using the following as information for fault diagnosis:
(a) layout information such as the inter-wiring distance between the fault signal line and the adjacent signal line, the parallel distance between the fault signal line and the adjacent signal line, and wiring widths of the signal lines;
(b) manufacturing process information influencing electric characteristics such as distances between wiring layers, wiring materials, and insulating layer materials; and
(c) timing information such as the directions of signal transitions on the signal lines, and the timing window of the signal transitions caused by the dynamic interference.